1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more particularly to a method of manufacturing a semiconductor device having a feature in a pretreatment step before entering a step o forming an upper conduction layer (metallization) in interconnection for a multilayered wiring structure of a highly integrated semiconductor device.
2. Description of Related Art
As integration degree of semiconductor devices such as in ULSI (Ultra Large Scale Integrated Circuits) has been increased and a design rule therefor has been refined, a multilayered wiring structure has been used frequently. In the multilayered wiring structure, a lower conduction layer and an upper conduction layer are electrically connected by way of a contact hole formed in the an interlayer insulation film. The size of the contact hole has also become finer and the opened diameter of a contact hole is about 0.24 .mu.m, for example, in a semiconductor device with a minimum design rule of 0.18 .mu.m. Since the thickness of the interlayer insulation film itself is about 10 .mu.m in view of an inter-wiring capacity and a withstand voltage, the aspect ratio of the contact hole reaches 4 or more.
For attaining a multilayered wiring structure of low resistivity and high reliability with a fine contact hole of high aspect ratio, it is indispensable for a pretreatment step of removing spontaneous oxide films and contaminants (hereinafter simply referred to as spontaneous oxide films) formed inevitably on the surface of the lower layer conduction layer exposed to the bottom of the contact hole, that is, a cleaning step.
The spontaneous oxide films on the surface of an impurity diffusion layer exposed at the bottom of a connection holes facing an impurity diffusion layer of a semiconductor substrate, for example, made of silicon as a lower conduction layer, that is, a contact hole mainly comprise silicon oxide and also contain etching residues, resist residues or adsorbed moisture. For removing the spontaneous oxide films, wet cleaning using an aqueous solution of diluted hydrofluoric acid has mainly been used so far. However, since the interlayer insulation film on the side wall of the contact hole is also etched isotropically to form an overhung shape, this gives rise to a problem of worsening the fillage of the contact plug or the upper layer wiring.
Further, in a contact hole having a fine opening diameter and a high aspect ratio, since a cleaning solution does not completely prevail as far as the inside of the contact hole, it gives rise to a problem of lowering the effect of removing spontaneous oxide films at the bottom of the contact hole.
Instead of the cleaning, dry cleaning using an adverse sputtering with Ar.sup.+ ions has been proposed and put to practical use for the pretreatment of via contact holes facing the lower layer wiring such as of Al series metal as the lower conduction layer. Since Ar.sup.+ ions can be controlled for the directionality by an electric field or the like, oxide films can be removed easily also from the bottom of a fine contact hole of high aspect ratio. However, upon removal of spontaneous oxide films on the surface of a lower layer wiring extended from the gate electrode, it has been pointed out a problem that gate insulation film suffers from destruction due to accumulation of charges by incident Ar.sup.+ ions.
Further, when the lower conduction layer is a shallow impurity diffusion layer formed to a semiconductor substrate, junction leakage may possibly be caused by damages due to incidence of Ar.sup.+ ions at a high ion energy.
In view of the above, the present inventors has already disclosed in Japanese Published Unexamined Patent Application No. Hei 6-260455, a soft etching method of using a plasma processing apparatus with low bias voltage and at high density plasma as a method of pretreatment upon forming an upper conduction layer in a contact hole. According to this method, cleaning with less damages is possible by using Ar.sup.+ ions at low energy. Further, a worry of etching rate reduction can be compensated with the improvement of plasma density.
However, in a present situation, in which the integration degree of a semiconductor device has further been increased and, for example, the thickness of the gate insulation film has been reduced to 10 nm or less and the depth of the impurity diffusion layer has also been made thinner, a cleaning method with less damages and higher stability is demanded. Further, severer cleaning is required in a case of forming the upper conduction layer with a high melting metal such as tungsten or a metal such as copper of low resistance by means of a CVD method or an electric field plating method in addition to sputtering of Al series metal.
Further, in a mass production line for semiconductor devices, when the number of processing batches is increased in a plasma processing apparatus for dry cleaning, conductive materials or organic materials removed by sputtering from the substrate to be processed are gradually deposited to the inner wall of the plasma processing apparatus. This lowers the insulation resistance value at the surface of the inner wall and makes actuation or continuation of plasma discharge instable if the resistance value is lowered to less than a predetermined level. As a result, this results in undesired effects on cleaning characteristics relative to the substrate to be processed, namely, etching off amount by the rare gas ions or scatterings thereof within the plane of the substrate to be processed and between the substrates to be processed, which results in lowering of yields of articles such as by increase of the contact resistance and instability thereof.